uRISC-T1 · ISA 1.0 · Document revision 4 · Theory
Smallsome MicroRISC
Small cores. Explicit resources. Accounted time.
- System
- 1 CPUlet · 64 cores
- Applications
- 60 cores; 4 reserved for system work
- Clock modes
- 0 / 50 / 250 MHz
- Local SRAM
- 12 × 1 KiB per core · 768 KiB total
- Shared RAM
- 256 MiB · RAM-resident framebuffer
- Graphics
- 1280 × 720 at 60 Hz · DVI-D
Architecture contract
31 assigned opcodes, explicit message/status operations, local memory slots and bounded resource transfers. External latency is represented by events and WAIT; the design does not promise zero wait time for RAM, peripherals or dependencies.
Scanout reads the framebuffer from shared RAM. Display and audio receive modeled service windows; USB 1.1 input and USB 2.0 storage remain outside the core instruction pipeline. Display throughput is not a guarantee of rendering performance.
One language frontend
Code and Symbols normalize to the same typed IR. Native integer operations use word; num is accepted only when its original semantics can be proven equivalent. Hardware FAULT and language Error are distinct. Endpoints, race timestamps and ownership transfer follow the shared 3.0 contract.
Bounded format work
RAU packets, RFXL regions, PMF0 roots and existing resource chunks provide candidate task boundaries. Dependencies, buffers, transfers and cancellation costs must be accounted for. A claimed hard deadline without bounded device stalls and cleanup is UNPROVEN.
Research boundary
The current scope is documentation only. No physical CPU, FPGA prototype, RTL verification, completed compiler or 8 × 8 Scrapbook app is delivered. Modeled timing is not measured silicon. Multi-CPUlet arrangements up to 4096 cores are future proposals, not the 64-core release scope.